The operand fields of RX-format instructions designate one or two registers, including an index register, and a virtual storage address (coded as an implicit address or an explicit address), with the following exception:
In BC branching instructions, a 4-bit branching mask (see 7 and TEN in the instructions labeled LAMBDAn below) with a value between 0 and 15, replaces the first register specification.
*--------*----*----*----*------------* |Op Code | R1 | X2 | B2 | D2 | *--------*----*----*----*------------* 0 8 12 16 20 31
Symbols used to represent registers (see REG1, INDEX, and BASE in the ALPHA2 instruction below) are assumed to be equated to absolute values between 0 and 15.
Symbols used to represent implicit addresses (see IMPLICIT in the instructions labeled GAMMAn below) can be either relocatable or absolute.
Symbols used to represent displacements (see DISPL in the instructions labeled BETA2 and LAMBDA1 below) in explicit addresses are assumed to be equated to absolute values between 0 and 4095.
Examples:
ALPHA1 L 1,200(4,10) ALPHA2 L REG1,200(INDEX,BASE) BETA1 L 2,200(,10) BETA2 L REG2,DISPL(,BASE) GAMMA1 L 3,IMPLICIT GAMMA2 L 3,IMPLICIT(INDEX) DELTA1 L 4,=F'33' LAMBDA1 BC 7,DISPL(,BASE) LAMBDA2 BC TEN,ADDRESS
When assembled, the object code for the instruction labeled ALPHA1, in hexadecimal, is:
5814A0C8
where:
When assembled, the object code for the instruction labeled GAMMA1, in hexadecimal, is:
5824xyyy
where:
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