The operand fields of RS-format instructions designate two registers, and a virtual storage address (coded as an implicit address or an explicit address).
*--------*----*----*----*------------* |Op Code | R1 | R3 | B2 | D2 | *--------*----*----*----*------------* 0 8 12 16 20 31
In the Insert Characters under Mask (ICM) and the Store Characters under Mask (STCM) instructions, a 4-bit mask (see X'E' and MASK in the instructions labeled DELTA1 and DELTA2 below), with a value between 0 and 15, replaces the second register specifications.
*--------*----*----*----*------------* |Op Code | R1 | M3 | B2 | D2 | *--------*----*----*----*------------* 0 8 12 16 20 31
Symbols used to represent registers (see REG4, REG6, and BASE in the instruction labeled ALPHA2 below) are assumed to be equated to absolute values between 0 and 15.
Symbols used to represent implicit addresses (see AREA and IMPLICIT in the instructions labeled BETA1 and DELTA2 below) can be either relocatable or absolute.
Symbols used to represent displacements (see DISPL in the instruction labeled BETA2 below) in explicit addresses are assumed to be equated to absolute values between 0 and 4095.
Examples:
ALPHA1 LM 4,6,20(12) ALPHA2 LM REG4,REG6,20(BASE) BETA1 STM 4,6,AREA BETA2 STM 4,6,DISPL(BASE) GAMMA1 SLL 2,15 DELTA1 ICM 3,X'E',1024(10) DELTA2 ICM REG3,MASK,IMPLICIT
When assembled, the object code for the instruction labeled ALPHA1, in hexadecimal, is:
9846C014
where:
When assembled, the object code for the instruction labeled DELTA1, in hexadecimal, is:
BF3EA400
where:
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