The term Intellectual Property (IP) block is used here to refer to a re-usable circuit element, or group of elements, that is used within multiple designs. These IP blocks usually provide some functional unit that is convenient to group – families with different characteristics (such as operations or performance) such as amplifiers, interface buffers, oscillators, signal modulators and demodulators.

It is assumed that there is a difference in responsibilities (activities and artifacts) when design content is supported across multiple usages. In many organizations this can be formalized through specialization of roles, the re-usable blocks being stored in libraries for reference and usage by others.

This scenario involves the update of an IP block (component, cell or design) and the update of a library release. In practice multiple IP blocks may be updated within a library release, the approach is repeatable, typically with some additional co-ordination between contributors and reviewers. The change may involve updates to IP block schematics or physical layout, such as for analog semiconductors.

IP Block or Library update Change requests may have their origins in multiple projects and some intermediate negotiation may well be required to priorities requests from multiple sources.

Depending on the maturity of the overall technology and designs, the rate of changes to IP blocks and libraries will vary. Organization often set a pace of library updates – this could be weekly in critical phases and monthly or even quarterly for stable blocks.

The current scenario focuses on analog IP blocks such as used in custom or analog-mixed signal semiconductor designs.

The major capabilities supported are:

• Change request definition, routing and tracking
• Design configuration management
• Cross-functional activity management
• Collaborative design review
• IP Block and Library release
• Integration between Electronic Design Automation circuit schematic and layout design
• Change and Configuration Management

The major business objectives addressed are:

• Engineering cost reduction
• Design cycle time reduction
• Library and IP Block release accuracy
• Increased re-use
• Engineering project risk reduction

Related scenarios not currently addressed directly:

• IP Block defect handling
• Library release planning including multiple related libraries
• IP Block variant handling
• Workload assignment across multiple contributors
• Support for IP Block analysis, verification and validation
• Notification of changes to IP Block consumers